1. Field of the Invention
The present invention relates to a semiconductor memory device wherein a difference in potential of data buses is increased during a write mode and this difference is reduced during a read mode.
2. Description of the Related Art
In a semiconductor memory device such as a MOS dynamic random access memory (DRAM) or a MOS static random access memory (SRAM), two complementary signals are written into or read from a memory cell array via a pair of data buses. During a write mode, the difference in potential of the data buses is increased to effectively carry out a write operation. On the other hand, during a read mode, the difference in potential of the data buses is reduced to improve the speed of a read operation, and the like. For this purpose, in a prior art semiconductor memory device, a write circuit, a restoring circuit, and an amplitude limiting circuit are separately provided. That is, the write circuit is used for enlarging the difference in potential of the data buses during a write mode. Also, the restoring circuit is used for reducing the difference in potential of the data buses when the control enters a read mode from the write mode. Further, the amplitude limiting circuit is used for maintaining the reduced difference in potential of the data buses. This prior art semiconductor memory device will be explained later in detail.
In the above-mentioned prior art, however, since the write circuit and the restoring circuit are separately provided, the entire device must be large, which hinders a high degree of integration of the device. Also, it is difficult to match the operation timing of the write circuit with that of the restoring circuit.